	org 0x0
start:
	; MUL A, B
	MOV A, #0x4
	MOV B, #0x6
	MUL AB
	MOV 0x20, A
	MOV 0x21, B
	MOV 0x22, PSW
	
	; MUL A, B
	MOV A, #0x15
	MOV B, #0x60
	MUL AB
	MOV 0x23, A
	MOV 0x24, B
	MOV 0x25, PSW
	
	; DIV AB
	MOV A, #0x15
	MOV B, #0x00
	DIV AB
	MOV 0x26, PSW

	; DIV AB
	MOV A, #0x67
	MOV B, #0x14
	DIV AB
	MOV 0x27, A
	MOV 0x28, B
	MOV 0x29, PSW
	
	; DA
	MOV A, #0x37
	ADD A, #0x36
	DA A
	MOV 0x2A, A
	
	MOV A, #0x37
	ADD A, #0x99
	DA A
	MOV 0x2B, A
	
	sjmp $
	
; for test
REG_SP		EQU	0x1000
REG_A		EQU	0x1001
REG_B		EQU	0x1002
REG_PSW		EQU	0x1003
REG_PC		EQU	0x1004
REG_DPTR	EQU	0x1005
CYCLE		EQU 0x1006
REG_R0		EQU	0x2000
REG_R1		EQU	0x2001
REG_R2		EQU	0x2002
REG_R3		EQU	0x2003
REG_R4		EQU	0x2004
REG_R5		EQU	0x2005
REG_R6		EQU	0x2006
REG_R7		EQU	0x2007
REG_END		EQU	0x2FFF
	org 0x600
	dW  REG_SP,		0x7
	dW  REG_A,		0x36
	dW  REG_B,		0x03
	dW  REG_PSW,	0xc0
	dW  REG_PC,		0x41
	dw  REG_DPTR,	0x00
	dw 	CYCLE,		55

	dw  0x20,		0x18
	dw  0x21,		0x00
	dw  0x22,		0x00
	dw  0x23,		0xE0
	dw  0x24,		0x07
	dw  0x25,		0x05
	dw  0x26,		0x05
	dw  0x27,		0x05
	dw  0x28,		0x03
	dw  0x29,		0x00
	dw  0x2A,		0x73
	dw  0x2B,		0x36

	dw  REG_END,	0
	end		